A unique constraint is used to randomize a group of variables such that no two members of the group have the same value.

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A unique constraint is used to randomize a group of variables such that no two members of the group have the same value.


If $monitor is called more than once, the last call will override previous one.Hence, this is illegal.It is defined in a class to initialize data members of the class.Th e new[ ] operator is used to allocate memory for a dynamic array.The size of the dynamic array that needs to be created is passed as an argument to th e new[ ] .What is the concept of forward declaration of a class in SystemVerilog?Sometimes a class might reference another class which is not fully defined in the compile order.This can cause a compile error.If two classe s Statistic s an d Packe t are defined in following order, then while compiling Statistics class, the definition of packet is not yet seen and compiler will fail.//full definition hereendclassTo avoid this problem, th e Packe t Class can be forward declared before the full definition.This concept is called forward declaration.//full definition hereendclassYes, interfaces are synthesizable.What is a clocking block and what are the benefits of using clocking blocks inside an interface?A clocking bloc k is a construct that assembles all the signals that are sampled or synchronized by a common clock and define their timing behaviors with respect to the clock.Following example illustrates a simple clocking block.The input skew defines how many time units before the clock event the signal is sampled.The output skew defines how many time units after the clock event the signal will be driven.A clocking block can be declared only inside a module or an interface.What is the difference between following two ways of specifying skews in a clocking block?In any event simulation, all the scheduled events at a specific time defines a time slot.The preponed region is executed only once and is the first phase of current time slot after advancing the simulation time.Sampling of signals from design for testbench input happens in this region.All blocking assignments are executed in Active region.If there are any assignments with #0 delays, those happen in the Inactive region.There is also a postponed region which is the last phase of current time slot.$monitor, $strobe and other similar events are scheduled for execution in this region.


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